User guide

You can share the reconfiguration interface among all the channels by turning on Share reconfiguration
interface when parameterizing the IP core. When this option is enabled, the IP core presents a single
reconfiguration interface for dynamic reconfiguration of all channels. Address bits [9:0] provide the
register address in the reconfiguration space of the selected channel. The remaining address bits of the
reconfiguration address specify the selected logical channel. For example, if there are four channels in the
Native PHY IP instance, reconfig_address[9:0] specifies the address and reconfig_address[11:10]
are binary encoded to specify the four channels. For example, 2'b01 in reconfig_address[11:10]
specifies logical channel 1.
The following figure shows the signals available when the Native PHY IP is configured for four channels
and the Share reconfiguration interface option is enabled.
Figure 6-11: Signals Available with Shared Native PHY Reconfiguration Interface
Native PHY IP
clk
reset
write
read
address
writedata
readdata
waitrequest
reconfig_clk
reconfig_reset
reconfig_write
reconfig_read
reconfig_address[11:0]
reconfig_writedata[31:0]
reconfig_readdata[31:0]
reconfig_waitrequest
Table 6-16: Reconfiguration Interface Ports with Shared Native PHY Reconfiguration Interface
The reconfiguration interface ports when Share reconfiguration interface is enabled. <N> represents the number
of channels.
Port Name Direction Clock Domain Description
reconfig_clk Input N/A Avalon clock. The clock frequency is
100-125 MHz.
reconfig_reset Input reconfig_clk Resets the Avalon interface.
reconfig_write Input reconfig_clk Write enable signal. Signal is active
high.
reconfig_read Input reconfig_clk Read enable signal. Signal is active high.
reconfig_address[log2<N>
+9:0]
Input reconfig_clk Address bus. The lower 10 bits specify
address and the upper bits specify the
channel.
reconfig_writedata[31:0] Input reconfig_clk A 32-bit data write bus. Data to be
written into the address indicated by
reconfig_address.
reconfig_readdata[31:0] Output reconfig_clk A 32-bit data read bus. Valid data is
placed on this bus after a read
operation. Signal is valid after
reconfig_waitrequest goes high and
then low.
UG-01143
2015.05.11
Ports and Parameters
6-25
Reconfiguration Interface and Dynamic Reconfiguration
Altera Corporation
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