User guide

Table 6-15: Register Map for Switching CDR Reference Clock Inputs
Native PHY Port Description Address Bits
cdr_refclk0 Represents logical refclk0.
Lookup register x16A[7:0]
stores the mapping from
logical refclk0 to the
physical refclk.
0x16A (Lookup Register) [7:0]
cdr_refclk1 Represents logical refclk1.
Lookup register x16B[7:0]
stores the mapping from
logical refclk1 to the
physical refclk.
0x16B (Lookup Register) [7:0]
cdr_refclk2 Represents logical refclk2.
Lookup register x16C[7:0]
stores the mapping from
logical refclk2 to the
physical refclk.
0x16C (Lookup Register) [7:0]
cdr_refclk3 Represents logical refclk3.
Lookup register x16D[7:0]
stores the mapping from
logical refclk3 to the
physical refclk.
0x16D (Lookup Register) [7:0]
cdr_refclk4 Represents logical refclk4.
Lookup register x16E[7:0]
stores the mapping from
logical refclk4 to the
physical refclk.
0x16E (Lookup Register) [7:0]
N/A CDR refclk selection MUX. 0x141 [7:0]
When performing a reference clock switch, note the logical reference clock to switch to and the respective
address and bits. After determining the logical reference clock, follow this procedure to switch to the
selected CDR reference clock:
1. Write 0x2 to address 0x0 of the channel.
2. Read from the lookup register and save the required 8-bit pattern. For example, switching to logical
refclk3 requires saving bits[7:0] at address 0x16D.
3. Perform a read-modify-write to bits [7:0] at address 0x141 using the 8-bit value obtained from the
lookup register.
4. Write 0x3 to address 0x0 of the channel.
Ports and Parameters
The reconfiguration interface is integrated in the Native PHY instance and the TX PLL instances.
Instantiate the Native PHY and the TX PLL IP cores in Qsys by clicking Tools > IP Catalog. You can
define parameters for IP cores by using the IP core-specific parameter editor. To expose the
reconfiguration interface ports, select the Enable dynamic reconfiguration option when parameterizing
the IP core.
6-24
Ports and Parameters
UG-01143
2015.05.11
Altera Corporation
Reconfiguration Interface and Dynamic Reconfiguration
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