User guide

Transceiver fPLL Port Description Address Bits
pll_refclk2 Represents logical refclk2 for MUX_1. Lookup
register x11F[4:0] stores the mapping from
logical refclk2 to the physical refclk for
MUX_1.
0x11F (Lookup
Register)
[4:0]
pll_refclk3 Represents logical refclk3 for MUX_1. Lookup
register x120[4:0] stores the mapping from
logical refclk3 to the physical refclk for
MUX_1.
0x120 (Lookup
Register)
[4:0]
pll_refclk4 Represents logical refclk4 for MUX_1. Lookup
register x121[4:0] stores the mapping from
logical refclk4 to the physical refclk for
MUX_1.
0x121 (Lookup
Register)
[4:0]
N/A fPLL refclk selection MUX_1. 0x11C [4:0]
Specify the logical reference clock and respective address and bits of the replacement clock when
performing a reference clock switch. Follow this procedure to switch to the selected reference clock:
1. Write 0x2 to address 0x0 of the PLL.
2. Read from the lookup register for MUX 0 and save the required 5-bit pattern. For example, switching
to logical refclk3 requires use of bits[4:0] at address 0x11A.
3. Perform a read-modify-write to bits [4:0] at address 0x114 using the 5-bit value obtained from the
lookup register.
4. Read from the lookup register for MUX 1 and save the required 5-bit pattern. For example, switching
to logical refclk3 requires use of bits[4:0] at address 0x120.
5. Perform a read-modify-write to bits [4:0] at address 0x11C using the 5-bit value obtained from the
lookup register.
6. Write 0x3 to address 0x0 of the PLL.
CDR and CMU Reference Clock Switching
You can use the reconfiguration interface to specify which reference clock source drives the CDR and
CMU PLL. The CDR supports clocking by up to five different reference clock sources.
Before initiating a reference clock switch, ensure that your CDR and CMU defines more than one
reference clock source. For the CDR, specify the parameter on the RX PMA tab during the Native PHY IP
parameterization. For the CMU, specify the Number of PLL reference clocks under the PLL tab when
parameterizing the CMU PLL.
The following table describes the addresses and bits for switching CDR and CMU reference clock inputs.
The number of exposed rx_cdr_refclk (CDR) or pll_refclk (CMU) varies according to the number of
reference clocks you specify. Use the CMU reconfiguration interface for switching the CMU reference
clock.
UG-01143
2015.05.11
CDR and CMU Reference Clock Switching
6-23
Reconfiguration Interface and Dynamic Reconfiguration
Altera Corporation
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