User guide

fPLL Reference Clock Switching
You can use the reconfiguration interface on the fPLL instance to specify which reference clock source
drives the fPLL. The fPLL supports clocking by up to five different reference clock sources. The flow to
select between the different reference clock sources is independent of the number of transmitter PLLs
specified in the reconfiguration interface.
Before initiating a reference clock switch, ensure that your fPLL instance defines more than one reference
clock source. Specify the Number of PLL reference clocks parameter on the PLL tab during fPLL
parameterization.
The following table shows the addresses and bits for switching between fPLL reference clock inputs. The
number of exposed pll_refclk ports varies according to the number of reference clocks you specify. Use
the fPLL reconfiguration interface for this operation.
Table 6-14: Register Map for Switching fPLL Reference Clock Inputs
Transceiver fPLL Port Description Address Bits
pll_refclk0 Represents logical refclk0 for MUX_0. Lookup
register x117[4:0] stores the mapping from
logical refclk0 to the physical refclk for
MUX_0.
0x117 (Lookup
Register)
[4:0]
pll_refclk1 Represents logical refclk1 for MUX_0.
Lookup register x118[4:0] stores the
mapping from logical refclk1 to the physical
refclk for MUX_0.
0x118 (Lookup
Register)
[4:0]
pll_refclk2 Represents logical refclk2 for MUX_0. Lookup
register x119[4:0] stores the mapping from
logical refclk2 to the physical refclk for
MUX_0.
0x119 (Lookup
Register)
[4:0]
pll_refclk3 Represents logical refclk3 for MUX_0. Lookup
register x11A[4:0] stores the mapping from
logical refclk3 to the physical refclk for
MUX_0.
0x11A (Lookup
Register)
[4:0]
pll_refclk4 Represents logical refclk4 for MUX_0. Lookup
register x11B[4:0] stores the mapping from
logical refclk4 to the physical refclk for
MUX_0.
0x11B (Lookup
Register)
[4:0]
N/A
fPLL refclk selection MUX_0.
0x114 [4:0]
pll_refclk0 Represents logical refclk0 for MUX_1. Lookup
register x11D[4:0] stores the mapping from
logical refclk0 to the physical refclk for
MUX_1.
0x11D (Lookup
Register)
[4:0]
pll_refclk1 Represents logical refclk1 for MUX_1. Lookup
register x11E[4:0] stores the mapping from
logical refclk1 to the physical refclk for
MUX_1.
0x11E (Lookup
Register)
[4:0]
6-22
fPLL Reference Clock Switching
UG-01143
2015.05.11
Altera Corporation
Reconfiguration Interface and Dynamic Reconfiguration
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