User guide

Table 6-11: Register Map for Switching Transmitter PLLs
Transceiver Native
PHY Port
Description Address Bits
tx_serial_clk0 Represents logical PLL0. Lookup register
x117[3:0] stores the mapping from logical
PLL0 to the physical PLL.
0x117 (Lookup
Register)
[3:0]
tx_serial_clk1 Represents logical PLL1. Lookup register
x117[7:4] stores the mapping from logical
PLL1 to the physical PLL.
0x117 (Lookup
Register)
[7:4]
tx_serial_clk2 Represents logical PLL2. Lookup register
x118[3:0] stores the mapping from logical
PLL2 to the physical PLL.
0x118 (Lookup
Register)
[3:0]
tx_serial_clk3 Represents logical PLL3. Lookup register
x118[7:4] stores the mapping from logical
PLL3 to the physical PLL.
0x118 (Lookup
Register)
[7:4]
N/A PLL selection MUX 0x111 [7:0]
When performing a PLL switch, you must specify the lookup register address and bit values you want to
switch to. The following procedure describes selection of a specific transmitter PLL when more than one
PLL is connected to a channel. To change the data rate of the CDR, follow the detailed steps for reconfi‐
guring channel and PLL blocks. After determining the logical PLL to switch to, follow this procedure to
switch to the desired transmitter PLL:
1. Write 0x2 to address 0x0 of the PLL.
2. Read from the appropriate lookup register address (refer to Table 6-11) and save the required 4-bit
pattern. For example, switching to logical PLL1 requires saving bits [7:4] of address 0x117.
3. Encode the 4-bit value read in the previous step into an 8-bit value according to the following table:
Table 6-12: Logical PLL Encoding
4-bit Logical PLL Bits 8-bit Mapping to Address 0x111
[3..0] {~logical_PLL_offset_readdata[3], logical_PLL_offset_readdata[1:0],logical_PLL_
offset_readdata[3], logical_PLL_offset_readdata[3:0] }
[7..4] {~logical_PLL_offset_readdata[7], logical_PLL_offset_readdata[5:4],logical_PLL_
offset_readdata[7], logical_PLL_offset_readdata[7:4] }
Note: For example, if reconfiguring to logical PLL1 then bits [7:4] is encoded to an 8-bit value {~bit[7],
bit[5:4], bit[7], bit[7:4]}.
4. Perform a read-modify-write to bits[7:0] of address 0x111 using the encoded 8-bit value.
5. Write 0x3 to address 0x5 of the PLL.
Related Information
Steps to Perform Dynamic Reconfiguration on page 6-12
Switching Reference Clocks
You can dynamically switch the input clock source for the ATX PLL, the fPLL, the CMU, and the CDR.
6-20
Switching Reference Clocks
UG-01143
2015.05.11
Altera Corporation
Reconfiguration Interface and Dynamic Reconfiguration
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