User guide

Table 6-4: Control and Status Register Memory Map for Embedded Reconfiguration Streamer
Reconfigu‐
ration
Address
(hex)
Reconfigu‐
ration Bit
Attribute
Name
Attribute
Description
Bit
Encoding
Transceiver Block Description
340
7 cfg_load Start
streaming
1'b1 Embedded
Reconfiguration
Streamer
Set to 1'b1 to initiate
streaming, self-
clearing bit
6 bcast_en Broadcast
enable
1'b1 Embedded
Reconfiguration
Streamer
Set to 1'b1 to
broadcast the same
profile to all the
channels
[2:0] cfg_sel Configurati
on profile
select
Direct
mapped
Embedded
Reconfiguration
Streamer
Binary encoding of
the configuration
Profile to stream
341 0 rcfg_busy Busy Status
bit
1'b1 Embedded
Reconfiguration
Streamer
Bit is set to:
• 1'b1—streaming is
in progress
• 1'b0—streaming is
complete
You can write to the address 0x340 at the same time to start the streaming, enable broadcasting, and select
the profile to be streamed. Different requests to multiple channels can be made simultaneously by writing
to the addresses of the desired channels through the user reconfiguration interface (shared or
independent). The reconfig_waitrequest signal will remain asserted after the reconfiguration
streaming is complete. When any of the masters (reconfiguration interface, ADME, or streamer) make the
next read or write request to that channel (slave), reconfig_waitrequest is deasserted.
You cannot use the embedded reconfiguration streamer to stream analog settings for the profiles. Refer to
“Steps to Perform Dynamic Reconfiguration” to change analog settings, TX PLL switching, and reference
clock switching.
Arbitration
The embedded reconfiguration streamer, reconfiguration interface, ADME, and ODI are all Avalon-MM
masters that arbitrate for control over the programmable space of each transceiver channel.
The embedded reconfiguration streamer has the highest priority, followed by the ODI, followed by the
reconfiguration interface, followed by the ADME. When two masters are trying to access the same
transceiver channel on the same clock cycle, the master with the highest priority is given access. The only
exception is when a lower-priority master is in the middle of a read/write operation and a higher-priority
master tries to access the same channel. In this case, the higher-priority master must wait until the lower-
priority master finishes the read/write operation.
UG-01143
2015.05.11
Arbitration
6-11
Reconfiguration Interface and Dynamic Reconfiguration
Altera Corporation
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