User guide

Figure 6-5: Arria 10 Native PHY with Embedded Streamer
User
Reconfiguration
Logic
Streamer
ADME
ODI
Channel
Configuration
Registers
Avalon-MM
Interface
Optional Reconfiguration Logic
(Capability, Control and Status,
PRBS Soft Accumulators,
ODI Acceleration Logic)
Arria 10 Transceiver
Arria 10 Native PHY
Debug Fabric
Host Link
Altera IP
Streamer connectivity to channel reconfiguration registers
ADME and ODI connectivity to channel reconfiguration
registers and optional soft registers
User Logic
Arbitration
Reconfiguration
Interface
You can control the embedded streamer block through the reconfiguration interface. Control and status
signals of the streamer block are memory mapped in the PHY’s soft control and status registers. These
embedded reconfiguration control and status registers are replicated for each channel. You cannot merge
reconfiguration interfaces across multiple IP cores when the embedded reconfiguration streamer is
enabled because the embedded reconfiguration streamer makes use of soft logic for control and status
registers.
For example, if the Native PHY IP has four channels—logical channel 0 to logical channel 3—and you
want to reconfigure logical channel 3 using the embedded reconfiguration streamer, you must write to the
control register of logical channel 3 using the reconfiguration interface with the appropriate bit settings.
Note:
The soft control and status registers at x340 and x341 are enabled when you enable the embedded
reconfiguration streamer in the Native PHY IP.
6-10
Embedded Reconfiguration Streamer
UG-01143
2015.05.11
Altera Corporation
Reconfiguration Interface and Dynamic Reconfiguration
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