User guide

Multiple Reconfiguration Profiles
You can optionally enable multiple configurations or profiles in the same Native PHY IP Parameter
Editor for performing dynamic reconfiguration of PCS parameters. This allows the IP Parameter Editor to
create, store, and analyze the parameter settings for multiple configurations or profiles.
When you enable multiple reconfiguration profiles feature, the Native PHY IP can generate configuration
files for all the profiles in the format desired (SystemVerilog package, MIF, or C header file). The configu‐
ration files are located in the <IP instance name>/reconfig/ subfolder of the IP instance with the configura‐
tion profile index added to the filename. For example, the configuration file for Profile 0 is stored as
<filename_CFG0.sv>. The Quartus II TimeQuest Timing Analyzer includes the necessary timing arcs for all
the configurations based on initial and target profiles. You can also generate reduced reconfiguration files
that contain only the attributes that differ between the multiple configured profiles. You can create up to
eight reconfiguration profiles (Profile 0 to Profile 7) at a time for each instance of the Native PHY IP.
The generated configuration files for each profile contain only PCS and a few functional PMA settings.
Also, the Quartus II TimeQuest Timing Analyzer will only include the necessary PCS timing arcs for all
the profiles. To perform a PMA reconfiguration such as TX PLL switching, CGB divider switching, or
reference clock switching, you must use the flow described in the “Steps to Perform Dynamic Reconfigu‐
ration”. Refer to Timing Closure Recommendations for more details about enabling multiple profiles and
running timing analyses.
You can use the multiple reconfiguration profiles feature without using the embedded reconfiguration
streamer feature. When using the multiple reconfiguration profiles feature by itself, you must write the
user logic to reconfigure all the entries that are different between the profiles while moving from one
profile to another.
Note:
You must ensure that none of the profiles in the Native PHY IP Parameter Editor gives error
messages, or the IP generation will fail. The Native PHY IP only validates the current active profile
dynamically. For example, if you store a profile with error messages in the Native PHY IP
Parameter Editor and load another profile without any error messages, the error messages will
disappear in the IP. You will then be allowed to generate the IP, but the generation will fail.
Related Information
• Steps to Perform Dynamic Reconfiguration on page 6-12
• Timing Closure Recommendations on page 6-55
Embedded Reconfiguration Streamer
You can optionally enable the embedded reconfiguration streamer in the Native PHY IP to automate the
reconfiguration operation.The embedded reconfiguration streamer is an Avalon-MM master that can
perform Avalon-MM transactions to access channel configuration registers in the transceiver. When you
enable the embedded streamer, the Native PHY IP will embed HDL code for reconfiguration profile
storage and reconfiguration control logic in the PHY IP files.
UG-01143
2015.05.11
Multiple Reconfiguration Profiles
6-9
Reconfiguration Interface and Dynamic Reconfiguration
Altera Corporation
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