User guide

Figure 6-3: Reading from the Reconfiguration Interface
119
XXXX
XXXX
reconfig_clk
reconfig_reset
reconfig_address
reconfig_read
reconfig_readdata
reconfig_waitrequest
reconfig_write
reconfig_writedata
VALID XXXX
Writing to the Reconfiguration Interface
Writing to the reconfiguration interface of the Transceiver Native PHY IP core or TX PLL IP core
changes the data value at a specific address. All writes to the reconfiguration interface must be read-
modify-write, because two or more features may share the same reconfiguration address. When two or
more features share the same reconfiguration address, one feature's data bits are interleaved with another
feature's data bits.
Writing to the reconfiguration interface involves the following steps:
1. Write 0x2 to address 0x0 of the channel or PLL to request access to the Avalon-MM interface.
2. Place a 10-bit feature address on the reconfig_address bus.
3. Assert the reconfig_read signal.
4. Wait for reconfig_waitrequest to transition from 1 to 0 and then read the 32-bit configuration data
value from the reconfig_readdata bus.
5. In the configuration data, modify only the necessary bits by masking out the non-relevant bits.
6. Place the same 10-bit feature address on the reconfig_address bus and place the modified configura‐
tion data value on the reconfig_writedata bus.
7. Assert the reconfig_write signal.
8. Write 0x3 to address 0x0 of the channel or the PLL to release the calibration bus.
UG-01143
2015.05.11
Writing to the Reconfiguration Interface
6-5
Reconfiguration Interface and Dynamic Reconfiguration
Altera Corporation
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