User guide

Interacting with the Reconfiguration Interface
Each transmit PLL and channel has a dedicated Avalon-MM slave interface. The transmit PLL instance
has a maximum of one reconfiguration interface. Unlike the PLL instance, the Native PHY instance can
specify multiple channels. You can use a dedicated reconfiguration interface for each channel or share a
single reconfiguration interface across all channels to perform dynamic reconfiguration.
Avalon-MM masters interact with the reconfiguration interface by performing Avalon read and write
operations to initiate dynamic reconfiguration of specific transceiver parameters. All read and write
operations must comply with Avalon-MM specifications.
Figure 6-2: Top-Level Signals of the Reconfiguration Interface
Arria 10 Native PHY IP
or
Arria 10 Transceiver PLL IP
reconfig_clk
reconfig_reset
reconfig_read
reconfig_write
reconfig_address
reconfig_writedata
reconfig_readdata
reconfig_waitrequest
To perform either a read or write operation through the reconfiguration interface, request access to
Avalon-MM interface by writing 0x2 to address 0x0 of the channel or the PLL. The access is granted after
the reconfig_waitrequest goes low. After you have access to the Avalon-MM interface, you can start
with all reconfiguration and recalibration requests. You must release the calibration bus after you have
completed all the requests to the Avalon-MM interface. To release the calibration bus, write a 0x3 to
address 0x0 of the channel or the PLL.
Related Information
• Avalon Interface Specifications
Reading from the Reconfiguration Interface
Reading from the reconfiguration interface retrieves the current value at a specific address. The read
operation involves the following steps:
1. Write 0x2 to address 0x0 of the channel or the PLL to request access to the Avalon-MM interface.
2. Place a 10-bit feature address on the reconfig_address bus.
3. Assert the reconfig_read signal.
4. Write 0x3 to address 0x0 of the channel or the PLL to release the calibration bus.
After the reconfig_read signal asserts, the reconfig_waitrequest signal asserts for a few
reconfig_clock cycles, then deasserts. This deassertion indicates the reconfig_readdata bus contains
valid data.
6-4
Interacting with the Reconfiguration Interface
UG-01143
2015.05.11
Altera Corporation
Reconfiguration Interface and Dynamic Reconfiguration
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