User guide

Related Information
• Interacting with the Reconfiguration Interface on page 6-4
• Reconfiguring Channel and PLL Blocks on page 6-3
• Configuration Files on page 6-6
• Multiple Reconfiguration Profiles on page 6-9
• Embedded Reconfiguration Streamer on page 6-9
• Embedded Debug Features on page 6-40
• Steps to Perform Dynamic Reconfiguration on page 6-12
Reconfiguring Channel and PLL Blocks
The following table lists some of the available dynamic reconfiguration features in Arria 10 devices.
Table 6-1: Arria 10 Dynamic Reconfiguration Feature Support
Reconfiguration Features
Channel Reconfiguration
PMA analog features
• V
OD
• Pre-emphasis
• Decision Feedback Equalization (DFE)
• On-Die Instrumentation (ODI)
TX PLL
• TX local clock dividers
• TX PLL switching
RX CDR
• RX CDR settings
• RX CDR reference clock switching
Datapath switching
• Standard, Enhanced, PCS Direct
PLL Reconfiguration
PLL settings
• Counters
PLL reference clock switching
Related Information
• Step 4: Reset Transceiver Channels or Transceiver PLLs
• Unsupported Features on page 6-58
UG-01143
2015.05.11
Reconfiguring Channel and PLL Blocks
6-3
Reconfiguration Interface and Dynamic Reconfiguration
Altera Corporation
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