User guide

master is connected to the Avalon-MM reconfiguration interface. Communication with the channel and
PLL reconfiguration interface requires an Avalon-compliant master.
Figure 6-1: Reconfiguration Interface in Arria 10 Transceiver IP Cores
Embedded Controller in FPGA
or Embedded Processor on PCB
Avalon-Compliant Master
Ch0: Avalon
Reconfiguration
Interface
Ch1: Avalon
Reconfiguration
Interface
Arria 10 Native PHY IP
Avalon
Reconfiguration
Interface
Arria 10 Transceiver PLL IP
The Arria 10 Transceiver Native PHY and Transmit PLL IP cores optionally allow you to save the
parameters you specify for the IP instances as configuration files. The configuration file stores addresses
and data values for the IP instance.
Two new optional features are provided in the Native PHY IP to automate the dynamic reconfiguration
process:
• Multiple reconfiguration profiles—enables multiple configurations or profiles in the same IP
Parameter Editor for dynamic reconfiguration. This allows the PHY IP to create, store, and analyze the
parameter settings for multiple configurations or profiles
• Embedded reconfiguration streamer—embeds the HDL for reconfiguration profile storage and
reconfiguration control logic in the PHY IP files
Altera Debug Master Endpoint (ADME) and optional reconfiguration logic are optional features provided
in Native PHY and Transmit PLL IP cores for test and debug. ADME is an embedded JTAG-based
Avalon-MM master that provides JTAG access to the IP. It can perform Avalon-MM transactions to
access soft and hard registers in the transceiver.
Optional reconfiguration logic is soft logic provided in the Native PHY and Transmit PLL IP cores to
facilitate embedded debug. This feature allows easy accessibility to debug features for the user logic and
debug tools.
On-Die Instrumentation (ODI) acceleration logic is an optional feature in the Native PHY IP that enables
you to embed soft logic for accelerating bit and error accumulation when using ODI. ODI monitors the
quality of the recovered analog signal and manipulates settings to enhance the quality of the recovered
signal.
6-2
Reconfiguration Interface and Dynamic Reconfiguration
UG-01143
2015.05.11
Altera Corporation
Reconfiguration Interface and Dynamic Reconfiguration
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