User guide

Bonded Byte Deserializer
The bonded byte deserializer is also available for channel-bundled applications such as PIPE. In this
configuration, the control signals of the byte deserializers of all the channels are bonded together. A
master channel controls all the other channels to prevent skew between the channels.
RX FIFO (Shared with Enhanced PCS and PCIe Gen3 PCS)
The RX FIFO interfaces between the PCS on the receiver side and the FPGA fabric and ensures reliable
transfer of data and status signals. It compensates for the phase difference between the FPGA fabric and
the PCS on the receiver side. The RX FIFO has a depth of 8. It operates in register FIFO and low latency
modes.
Figure 5-45: RX FIFO Block Diagram
RX
FIFO
Datapath to FPGA Fabric
or PIPE Interface
rx_coreclkin
Datapath from
Byte Deserializer, 8B/10B Decoder,
Rate Match FIFO, or Deserializer
wr_clk rd_clk
Parallel clock
(recovered)
from clock divider
rx_clkout
RX FIFO Low Latency Mode
The low latency mode incurs two to three cycles of latency when connecting it with the FPGA fabric. The
FIFO empty and the FIFO full threshold values are made closer so that the depth of the FIFO decreases,
which in turn decreases the latency.
RX FIFO Register Mode
The register mode bypasses the FIFO functionality to eliminate the FIFO latency uncertainty for applica‐
tions with stringent latency requirements. This is accomplished by tying the read clock of the FIFO with
its write clock. The register mode incurs only one clock cycle of latency when interfacing to the FPGA
fabric.
Arria 10 PCI Express Gen3 PCS Architecture
Arria 10 architecture supports the PCIe Gen3 specification. Altera provides two options to implement the
PCI Express solution:
• You can use the Altera Hard IP solution. This complete package provides both the MAC layer and the
physical (PHY) layer functionality.
• You can implement the MAC in the FPGA core and connect this MAC to the transceiver PHY
through the PIPE interface.
UG-01143
2015.05.11
Bonded Byte Deserializer
5-53
Arria 10 Transceiver PHY Architecture
Altera Corporation
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