User guide

Transmitter Datapath....................................................................................................................5-19
Receiver Datapath..........................................................................................................................5-29
Arria 10 Standard PCS Architecture.......................................................................................................5-37
Transmitter Datapath....................................................................................................................5-37
Receiver Datapath..........................................................................................................................5-42
Arria 10 PCI Express Gen3 PCS Architecture.......................................................................................5-53
Transmitter Datapath....................................................................................................................5-54
Receiver Datapath..........................................................................................................................5-55
PIPE Interface.................................................................................................................................5-56
Reconfiguration Interface and Dynamic Reconfiguration ............................... 6-1
Reconfiguring Channel and PLL Blocks...................................................................................................6-3
Interacting with the Reconfiguration Interface.......................................................................................6-4
Reading from the Reconfiguration Interface............................................................................... 6-4
Writing to the Reconfiguration Interface.....................................................................................6-5
Configuration Files......................................................................................................................................6-6
Multiple Reconfiguration Profiles.............................................................................................................6-9
Embedded Reconfiguration Streamer.......................................................................................................6-9
Arbitration..................................................................................................................................................6-11
Steps to Perform Dynamic Reconfiguration..........................................................................................6-12
Direct Reconfiguration Flow....................................................................................................................6-13
Changing PMA Analog Parameters............................................................................................6-13
Changing CTLE Settings in Manual Mode................................................................................6-15
Enabling and Disabling Loopback Modes..................................................................................6-15
IP Guided Reconfiguration Flow.............................................................................................................6-18
Reconfiguration Flow for Special Cases..................................................................................................6-19
Switching Transmitter PLL ..........................................................................................................6-19
Switching Reference Clocks..........................................................................................................6-20
Ports and Parameters.................................................................................................................................6-24
Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks.........................................6-29
On-Die Instrumentation...........................................................................................................................6-31
Using ODI to Build On-chip Eye Process..................................................................................6-38
Start Pattern Checker ................................................................................................................... 6-39
Embedded Debug Features.......................................................................................................................6-40
Altera Debug Master Endpoint....................................................................................................6-40
Optional Reconfiguration Logic..................................................................................................6-40
Using Data Pattern Generators and Checkers.......................................................................................6-47
Using PRBS and Square Wave Data Pattern Generator and Checker....................................6-47
Using Pseudo Random Pattern Mode.........................................................................................6-54
Timing Closure Recommendations........................................................................................................ 6-55
Unsupported Features...............................................................................................................................6-58
Arria 10 Transceiver Register Map..........................................................................................................6-58
Calibration...........................................................................................................7-1
Reconfiguration Interface and Arbitration with PreSICE Calibration Engine ..................................7-1
Calibration Registers................................................................................................................................... 7-2
Avalon-MM Interface Arbitration Registers................................................................................7-3
Arria 10 Transceiver PHY Overview
TOC-5
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