User guide

Byte Deserializer
The byte deserializer allows the transceiver to operate at data rates higher than those supported by the
FPGA fabric. It deserializes the recovered data by multiplying the data width two or four times, depending
upon the deserialization mode selected. The byte deserializer is optional in designs that do not exceed the
FPGA fabric interface frequency upper limit. You can bypass the byte deserializer by disabling it in the
Quartus II Transceiver Native PHY. The byte deserializer operates in disabled, deserialize x2, or
deserialize x4 modes.
Figure 5-44: Byte Deserializer Block Diagram
Byte
Deserializer
Datapath from the
8B/10B Decoder,
Rate Match FIFO,
or Word Aligner
Datapath to the RX FIFO
/2,
/4
Low speed
parallel clock
Byte Deserializer Disabled Mode
In disabled mode, the byte deserializer is bypassed. The data from the 8B/10B decoder, rate match FIFO,
or word aligner is directly transmitted to the RX FIFO, depending on whether or not the 8B/10B decoder
and rate match FIFO are enabled. Disabled mode is used in low speed applications such as GigE, where
the FPGA fabric and the PCS can operate at the same clock rate.
Byte Deserializer Deserialize x2 Mode
The deserialize x2 mode is used in high-speed applications such as the PCIe Gen1 or Gen2 protocol
implementation, where the FPGA fabric cannot operate as fast as the TX PCS.
In deserialize x2 mode, the byte deserializer deserializes 8-bit, 10-bit (when the 8B/10B encoder is not
enabled), 16-bit, and 20-bit (when the 8B/10B encoder is not enabled) input data into 16-bit, 20-bit, 32-
bit, and 40-bit data, respectively. As the parallel data width from the word aligner is doubled, the clock
rate is halved.
Byte Deserializer Deserialize x4 Mode
The deserialize x4 mode is used in high-speed applications where the FPGA fabric cannot operate as fast
as the TX PCS.
In deserialize x4 mode, the byte deserializer deserializes 8-bit data into 32-bit data. As the parallel data
width from the word aligner is quadrupled, the clock rate is divided four times.
5-52
Byte Deserializer
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Architecture
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