User guide

8B/10B Decoder Control Code Encoding
Figure 5-43: 8B/10B Decoder in Control Code Group Detection
datain[9:0]
dataout[7:0]
D31.5D3.4 D24.3 D28.5 K28.5 D15.0 D0.0
BF0083 78 BC BC 0F
tx_clkout
rx_datak
datain[19:10]
tx_clkout
datain[9:0]
rx_datak[1:0]
dataout[15:0]
When the PCS-PMA Interface Width is 10 Bits
When the PCS-PMA Interface Width is 20 Bits
TX
RX
D15.0D3.4 D28.5 D15.0 D3.4 D3.4 D28.5 D3.4
D15.0D24.3 K28.5 D15.0 D3.4 D24.3 K28.5 D3.4
00 01 00 00 01 00
16’h8378 16’hBCBC 16’h0F0F 16’h8383 16’h8378 16’hBCBC 16’h0F0F 16’h8383
83
RX
TX
D3.4
The 8B/10B decoder indicates whether the decoded 8-bit code group is a data or control code group on
rx_datak . If the received 10-bit code group is one of the 12 control code groups (/Kx.y/) specified in the
IEEE 802.3 specification, rx_datak is driven high. If the received 10-bit code group is a data code group
(/Dx.y/), rx_datak is driven low.
8B/10B Decoder Running Disparity Checker Feature
Running disparity checker resides in 8B/10B decoder module. This checker checks the current running
disparity value and error based on the rate match output. rx_runningdisp and rx_disperr indicate
positive or negative disparity and disparity errors, respectively.
Pseudo-Random Binary Sequence (PRBS) Checker
Note:
Refer to the PRBS Checker section in the Enhanced PCS Architecture chapter.
Related Information
• Arria 10 Enhanced PCS Architecture on page 5-18
UG-01143
2015.05.11
8B/10B Decoder Control Code Encoding
5-51
Arria 10 Transceiver PHY Architecture
Altera Corporation
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