User guide

from the PMA is a 10-bit data width, the bit reversal feature switches bit [0] with bit [9], bit [1] with bit
[8], and so on. For example, if the 10-bit data is 1000010011, the bit reversal feature, when enabled,
changes the data to 1100100001.
Word Aligner RX Byte Reversal Feature
The RX byte reversal feature is available only when the PCS-PMA interface width is 16 bits or 20 bits. This
feature reverses the order of the data received from the PMA. RX byte reversal reverses the LSByte of the
received data with its MSByte and vice versa. If the data received is 20-bits, bits[0..9] are swapped with
bits[10..20] so that the resulting 20-bit data is [[10..20],[0..9]]. For example, if the 20-bit data is
11001100001000011111, the byte reversal feature changes the data to 10000111111100110000.
RX Polarity Inversion Feature
The RX polarity inversion feature inverts each bit of the data received from the PMA. If the data received
is a 10-bit data. Bit[0] content is inverted to its complement, ~bit[0], bit[1] is inverted to its complement,
~bit[1], bit[2] is inverted to its complement, ~bit[2], and so on. For example, if the 10-bit data is
1111100000, the polarity inversion feature inverts it to 0000011111.
Rate Match FIFO
The rate match FIFO compensates for the frequency differences between the local clock and the recovered
clock up to ± 300 ppm by inserting and deleting skip/idle characters in the data stream. The rate match
FIFO has several different protocol specific modes of operation. All of the protocol specific modes depend
upon the following parameters:
• Rate match deletion—occurs when the distance between the write and read pointers exceeds a certain
value due to write clock having a higher frequency than the read clock.
• Rate match insertion—occurs when the distance between the write and the read pointers becomes less
than a certain value due to the read clock having a higher frequency than the write clock.
• Rate match full—occurs when the write pointer wraps around and catches up to the slower-advancing
read pointer.
• Rate match empty—occurs when the read pointer catches up to the slower-advancing write pointer.
Rate match FIFO operates in six modes:
• Basic single width
• Basic double width
• GigE
• PIPE
• PIPE 0 ppm
• PCIe
Related Information
• How to Implement the Basic Rate Match Protocol Using the Arria 10 Transceiver Native PHY IP
Core
For more information about implementing rate match FIFO for each mode.
• Rate Match FIFO in Basic (Single Width) Mode on page 2-298
For more information about implementing rate match FIFO in basic single width mode.
UG-01143
2015.05.11
Word Aligner RX Byte Reversal Feature
5-49
Arria 10 Transceiver PHY Architecture
Altera Corporation
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