User guide

a new word boundary. If rx_std_wa_patternalign is deasserted, the word aligner maintains the current
word boundary even when it sees the word alignment pattern in a new word boundary.
The rx_syncstatus and rx_patterndetect signals, with the same latency as the datapath, are forwarded
to the FPGA fabric to indicate the word aligner status.
After receiving the first word alignment pattern after rx_std_wa_patternalign is asserted, both
rx_syncstatus and rx_patterndetect are driven high for one parallel clock cycle. Any word alignment
pattern received thereafter in the same word boundary causes only rx_patterndetect to go high for one
clock cycle. Any word alignment pattern received thereafter in a different word boundary causes the word
aligner to re-align to the new word boundary only if rx_std_wa_patternalign is asserted. The word
aligner asserts rx_syncstatus for one parallel clock cycle whenever it re-aligns to the new word
boundary.
Word Aligner Synchronous State Machine Mode
In synchronous state machine mode, when the programmed number of valid synchronization code
groups or ordered sets is received, rx_syncstatus is driven high to indicate that synchronization is
acquired. The rx_syncstatus signal is constantly driven high until the programmed number of
erroneous code groups is received without receiving intermediate good groups, after which
rx_syncstatus is driven low.
The word aligner indicates loss of synchronization (rx_syncstatus remains low) until the programmed
number of valid synchronization code groups are received again.
Word Aligner Deterministic Latency Mode
In deterministic latency mode, the state machine removes the bit level latency uncertainty. The deserial‐
izer of the PMA creates the bit level latency uncertainty as it comes out of reset.
The PCS performs pattern detection on the incoming data from the PMA. The PCS aligns the data, after it
indicates to the PMA the number of serial bits to clock slip the boundary.
If the incoming data has to be realigned, rx_std_wa_patternalign must be reasserted to initiate another
pattern alignment. Asserting rx_std_wa_patternalign can cause the word align to lose synchronization
if already achieved. This may cause rx_syncstatus to go low.
Table 5-10: PCS-PMA Interface Widths and Protocol Implementations
PCS-PMA Interface Width Protocol Implementations
8 Basic
10
• Basic
• Basic rate match
• CPRI
• PCIe Gen1 and Gen2
• GigE
16 Basic
5-44
Word Aligner Synchronous State Machine Mode
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Architecture
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