User guide

Figure 2-5: Transceiver Native PHY IP Core Ports and Functional Blocks
Reconfiguration
Registers
Enhanced PCS
Transmit and Receive Clocks
Standard PCS
PCIe Gen3
PCS
Transmit
PMA
Receive
PMA
Reset Signals
Transmit Parallel Data
Reconfiguration Interface
Transmit Serial Data
Receive Serial Data
Receive Parallel Data
PCS-Direct
Nios II
Calibration
Calibration Signals
Figure 2-6: Transceiver Native PHY IP Core Parameter Editor
Note:
Although the Quartus II software provides legality checks, the supported FPGA fabric to PCS
interface widths and the supported data rates are pending characterization.
2-18
Using the Arria 10 Transceiver Native PHY IP Core
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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