User guide

8B/10B Encoder Bit Reversal Feature
The bit reversal feature reverses the order of the bits of the input data. Bit reversal is performed at the
output of the 8B/10B Encoder and is available even when the 8B/10B Encoder is disabled. For example, if
the input data is 20-bits wide, bit reversal switches bit [0] with bit [19], bit [1] with bit [18] and so on.
8B/10B Encoder Byte Reversal Feature
The byte reversal feature is available only when the PCS-PMA interface width is 16 bits or 20 bits. Byte
reversal is performed at the output of the 8B/10B Encoder and is available even when the 8B/10B Encoder
is disabled. This feature swaps the LSByte with the MSByte and vice-versa. For example, when the PCS-
PMA interface width is 16-bits, [7:0] bits (LSByte) gets swapped with [15:8] bits (MSByte) and [15:8] bits
(MSByte) gets swapped with [7:0] bits (LSByte). As a result, the 16-bit bus becomes MSB to LSB, bits[7:0]
to bits[15:8].
Polarity Inversion Feature
The polarity inversion feature is used in situations where the positive and the negative signals of a serial
differential link are erroneously swapped during board layout. This feature can be controlled by the
tx_polinv port after enabling "Enable TX Polarity Inversion" option under Standard PCS. The polarity
inversion feature inverts the value of each bit of the input data. For example, if the input data is 00101001,
then the data gets changed to 11010110 after polarity inversion.
Pseudo-Random Binary Sequence (PRBS) Generator
Note:
Refer to the PRBS Generator section in the Enhanced PCS Architecture chapter.
Related Information
• Arria 10 Enhanced PCS Architecture on page 5-18
TX Bit Slip
The TX bit slip allows the word boundary to be controlled by tx_std_bitslipboundarysel. The TX bit
slip feature is used in applications, such as CPRI, which has a data rate greater than 6 Gbps. The
maximum number of the supported bit slips is PCS data width-1 and the slip direction is from MSB to
LSB and from current to previous word.
Receiver Datapath
Word Aligner
The word aligner receives the serial data from the PMA and realigns the serial data to have the correct
word boundary according to the word alignment pattern configured. This word alignment pattern can be
7, 8, 10, 16, 20, 32 and 40 bits in length.
5-42
8B/10B Encoder Bit Reversal Feature
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Architecture
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