User guide

Figure 5-37: TX FIFO Block Diagram
TX
FIFO
Datapath from FPGA Fabric
or PIPE Interface
tx_coreclkin
tx_clkout
Datapath to Byte Serializer,
8B/10B Encoder,
or Serializer
wr_clkrd_clk
The TX FIFO read port is clocked by the low speed parallel clock and its write port is clocked by either
tx_clkout or tx_coreclkin. The tx_clkout signal is used when only one channel is being used. The
tx_coreclkin signal is used when using multiple channels. The TX FIFO is shared with PCIe Gen3 and
Enhanced PCS data paths.
TX FIFO Low Latency Mode
The low latency mode incurs two to three cycles of latency (latency uncertainty) when connecting it with
the FPGA fabric. The FIFO empty and the FIFO full threshold values are made closer so that the depth of
the FIFO decreases, which in turn decreases the latency.
TX FIFO Register Mode
The register mode bypasses the FIFO functionality to eliminate the FIFO latency uncertainty for applica‐
tions with stringent latency requirements. This is accomplished by tying the read clock of the FIFO with
its write clock. The register mode incurs only one clock cycle of latency when interfacing to the FPGA
fabric.
TX FIFO Fast Register Mode
This mode allows a higher maximum frequency (f
MAX
) between the FPGA fabric and the TX PCS by
enabling the optional fast register interface with additional latency.
Byte Serializer
In certain applications, the FPGA fabric interface cannot operate at the same clock rate as the transmitter
channel (PCS) because the transmitter channel is capable of operating at higher clock rates compared to
the FPGA fabric. The byte serializer allows the transmitter channel to operate at higher data rates while
keeping the FPGA fabric interface clock rate below its maximum limit. This is accomplished by increasing
the channel width two or four times (FPGA fabric-to-PCS interface width) and halving/dividing by 4 the
core the clock rate. The byte serializer is disabled, or operates in Serialize x2 or Serialize x4 modes.
5-38
TX FIFO Low Latency Mode
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Architecture
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