User guide

Arria 10 Standard PCS Architecture
The standard PCS can operate at a data rate up to 12 Gbps. Protocols such as PCI-Express, CPRI 4.2+,
GigE, IEEE 1588 are supported in Hard PCS while the other protocols can be implemented using Basic/
Custom (Standard PCS) transceiver configuration rules.
Figure 5-36: Standard PCS Datapath Diagram
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Receiver PMA
Word Aligner
Deserializer
CDR
Receiver Standard PCS
Transmitter Standard PCS
Transmitter PMA
Serializer
tx_serial_data
rx_serial_data
FPGA
Fabric
TX
FIFO
Byte Serializer
8B/10B Encoder
PRBS
Generator
TX Bit Slip
/2, /4
/2, /4
Parallel Clock
Serial Clock
Parallel and Serial Clock
Parallel and Serial Clock
Clock Divider
rx_pma_div_clkout
Serial Clock
Clock Generation Block (CGB)
ATX PLL
CMU PLL
fPLL
tx_coreclkin
rx_coreclkin
rx_clkout or
tx_clkout
Parallel Clock
(Recovered)
Parallel Clock
(From Clock
Divider)
tx_clkout
tx_clkout
tx_clkout
rx_clkout
PRBS
Verifier
tx_pma_div_clkout
Transmitter Datapath
TX FIFO (Shared with Enhanced PCS and PCIe Gen3 PCS)
The TX FIFO interfaces between the transmitter PCS and the FPGA fabric and ensures reliable transfer of
data and status signals. It compensates for the phase difference between the FPGA fabric clock and
tx_clkout (the low-speed parallel clock). The TX FIFO has a depth of 8 and operates in low latency
mode, register mode, and fast register mode.
UG-01143
2015.05.11
Arria 10 Standard PCS Architecture
5-37
Arria 10 Transceiver PHY Architecture
Altera Corporation
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