User guide

Figure 5-35: IDLE Word Insertion
This figure shows the insertion of IDLE words in the receiver data stream.
Idle Inserted
Before Insertion
After Insertion
FD000000000004AEh BBBBBB9CDDDDDD9Ch 0707070707070707h 00000000000000FBh
FD000000000004AEh BBBBBB9CDDDDDD9Ch 00000000000000FBh AAAAAAAAAAAAAAAAhrx_parallel_data
rx_parallel_data
Basic Mode
In Basic mode, the RX FIFO operates as an elastic buffer. The FIFO write enable is controlled by gearbox
data valid, which is a function of gearbox input and output data width. You can monitor the
rx_enh_fifo_pempty and rx_enh_fifo_pfull flags to determine whether to read from the FIFO or not.
RX KR FEC Blocks
KR FEC Block Synchronization
You can obtain FEC block delineation for the RX KR FEC by locking onto correctly received FEC blocks
with the KR FEC block synchronization.
Note:
The KR FEC block synchronization is available to implement the 10GBASE-KR protocol.
KR FEC Descrambler
The KR FEC descrambler block descrambles received data to regenerate unscrambled data using the x
58
+
x
39
+1 polynomial. Before the block boundary in the KR FEC sync block is detected, the data at the input
of the descrambler is sent directly to the KR FEC decoder. When the boundary is detected, the aligned
word from the KR FEC sync block is descrambled with the Psuedo Noise (PN) sequence and then sent to
the KR FEC decoder.
KR FEC Decoder
The KR FEC decoder block performs the FEC (2112, 2080) decoding function by analyzing the received
32 65-bit blocks for errors. It can correct burst errors of 11 bits or less per FEC block.
KR FEC RX Gearbox
The KR FEC RX gearbox block adapts the PMA data width to the larger bus width of the PCS channel. It
supports a 64:65 ratio.
Transcode Decoder
The transcode decoder block performs the 65-bit to 64B/66B reconstruction function by regenerating the
64B/66B synchronization header.
5-36
Basic Mode
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Architecture
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