User guide

Figure 5-32: RX FIFO as Interlaken Deskew FIFO
User
Deskew
FSM
FPGA Fabric Interface
rx_enh_fifo_align_clr
rx_enh_fifo_rd_en
rx_enh_fifo_pempty
rx_enh_fifo_pfull
RX FIFO
10GBASE-R Mode
In 10GBASE-R mode, the RX FIFO operates as a clock compensation FIFO. When the block synchronizer
achieves block lock, data is sent through the FIFO. Idle ordered sets (OS) are deleted and Idles are inserted
to compensate for the clock difference between the RX low speed parallel clock and the FPGA fabric clock
(±100 ppm for a maximum packet length of 64,000 bytes).
Idle OS Deletion
Deletion of Idles occurs in groups of four OS (when there are two consecutive OS) until the
rx_enh_fifo_rd_pempty flag deasserts. Every word—consisting of a lower word (LW) and an upper
word (UW)—is checked for whether it can be deleted by looking at both the current and previous words.
For example, the current LW can be deleted if it is Idle and the previous UW is not a Terminate.
Table 5-7: Conditions Under Which a Word Can be Deleted
In this table X=don’t care, T=Terminate, I=Idle, and OS=order set.
Deletable Case Word Previous Current Output
Lower Word
1
UW !T X !T X
LW X I X X
2
UW OS X OS X
LW X OS X X
Upper Word
1
UW X I X X
LW X !T X !T
2
UW X OS X X
LW X OS X OS
If only one word is deleted, data shifting is necessary because the datapath is two words wide. After two
words have been deleted, the FIFO stops writing for one cycle and a synchronous flag (rx_control[8])
appears on the next block of 8-byte data. There is also an asynchronous status signal rx_enh_fifo_del,
which does not go through the FIFO.
5-34
10GBASE-R Mode
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Architecture
Send Feedback