User guide

The RX FIFO supports the following modes:
• Phase Compensation mode
• Register mode
• Interlaken mode (deskew FIFO)
• 10GBASE-R mode (clock compensation FIFO)
• Basic mode (elastic buffer FIFO)
Phase Compensation Mode
The RX FIFO compensates for the phase difference between the read clock and write clocks. rx_clkout
(RX parallel low-speed clock) clocks the write side of the RX FIFO. rx_coreclkin (FPGA fabric clock) or
rx_clkout clocks the read side of the RX FIFO.
When phase compensation is used in double-width mode, the FPGA data width is doubled to allow the
FPGA fabric clock to run at half rate, similar to the TX FIFO phase compensation in double-width mode.
Register Mode
In Register mode, rx_parallel_data (data), rx_control indicates whether rx_parallel_data is a data
or control word, and rx_enh_data_valid (data valid) are registered at the FIFO output. The RX FIFO in
register mode has one register stage or one parallel clock latency.
Note: Altera recommends a minimum of 32-words for the soft FIFO depth in the FPGA fabric for the
following conditions:
• When the Enhanced PCS RX FIFO is set to register mode.
• When using the recovered clock to drive the core logics.
• When there is no soft FIFO being generated along with the IP Catalog.
Interlaken Mode
In Interlaken mode, the RX FIFO operates as an Interlaken deskew FIFO. To implement the deskew
process, implement an FSM that controls the FIFO operation based on available FPGA input and output
flags.
For example, after frame lock is achieved, data is written after the first alignment word (SYNC word) is
found on that channel. As a result, rx_enh_fifo_pempty (FIFO partially empty flag ) of that channel goes
low. You must monitor the rx_enh_fifo_pempty and rx_enh_fifo_pfull flags of all channels. If
rx_enh_fifo_pempty flags from all channels deassert before any rx_enh_fifo_pfull flag asserts, which
implies alignment word has been found on all lanes of the link, you start reading from all the FIFOs by
asserting rx_enh_fifo_rd_en. Otherwise, if a rx_enh_fifo_pfull flag from any channel goes high
before a rx_enh_fifo_pempty flag deassertion on all channels, you must reset the FIFO by toggling the
rx_enh_fifo_align_clr signal and repeating the process.
UG-01143
2015.05.11
Phase Compensation Mode
5-33
Arria 10 Transceiver PHY Architecture
Altera Corporation
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