User guide

Figure 5-31: PRP Verifier
Error
Counter
Test Pattern
Detect
Pseudo Random
Verifier
error_count
Descrambler
Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for configuration details.
Related Information
• Reconfiguration Interface and Dynamic Reconfiguration on page 6-1
10GBASE-R Bit-Error Rate (BER) Checker
The 10GBASE-R BER checker block is designed in accordance with the 10GBASE-R protocol specifica‐
tion as described in IEEE 802.3-2008 clause-49. After block lock synchronization is achieved, the BER
checker starts to count the number of invalid synchronization headers within a 125-μs period. If more
than 16 invalid synchronization headers are observed in a 125-μs period, the BER checker provides the
status signal rx_enh_highber to the FPGA fabric, indicating a high bit error rate condition.
When the optional control input rx_enh_highber_clr_cnt is asserted, the internal counter for the
number of times the BER state machine has entered the "BER_BAD_SH" state is cleared.
When the optional control input rx_enh_clr_errblk_count is asserted, the internal counter for the
number of times the RX state machine has entered the "RX_E" state for the 10GBASE-R protocol is
cleared. In modes where the FEC block in enabled, the assertion of this signal resets the status counters
within the RX FEC block.
Note:
The 10GBASE-R BER checker is available to implement the 10GBASE-R protocol.
Interlaken CRC-32 Checker
The Interlaken CRC-32 checker verifies that the data transmitted has not been corrupted between the
transmit PCS and the receive PCS. The CRC-32 checker calculates the 32-bit CRC for the received data
and compares it against the CRC value that is transmitted within the diagnostic word. rx_enh_crc32_err
(CRC error signal) is sent to the FPGA fabric.
Enhanced PCS RX FIFO
The Enhanced PCS RX FIFO is designed to compensate for the phase and/or clock difference between the
receiver channel PCS and the FPGA fabric. It can operate as a phase-compensation, clock-compensation,
elastic buffer, or a deskew FIFO in Interlaken mode. The RX FIFO has a width of 74 bits and a depth of 32
words for all protocols.
5-32
10GBASE-R Bit-Error Rate (BER) Checker
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Architecture
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