User guide

PRBS Pattern 10 bit PCS-PMA width 64 bit PCS-PMA width
PRBS15: x
15
+ x
14
+ 1 Yes
PRBS23: x
23
+ x
18
+ 1 Yes
PRBS31: x
31
+ x
28
+ 1 Yes
Figure 5-30: PRBS9 Verify Serial Implementation
S0 S1 S4 S5 S8
PRBS Error
PRBS datain
The PRBS checker has the following control and status signals available to the FPGA fabric:
• rx_prbs_done—Indicates the PRBS sequence has completed one full cycle. It stays high until you reset
it with rx_prbs_err_clr.
• rx_prbs_err—Goes high if an error occurs. This signal is pulse-extended to allow you to capture it in
the RX FPGA CLK domain.
• rx_prbs_err_clr—Used to reset the rx_prbs_err signal.
The RX datapath does not include a checker for the square wave.
Enable the PRBS checker control and status ports through the Native PHY IP Parameter Editor in the
Quartus II software.
Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for configuration details.
Related Information
• Reconfiguration Interface and Dynamic Reconfiguration on page 6-1
Pseudo Random Pattern Verifier
The Pseudo Random Pattern (PRP) verifier is available for 10GBASE-R and 10GBASE-R 1588 protocol
modes. The PRP verifier block operates in conjunction with the descrambler. The PRP verifier monitors
the output of the descrambler when block synchronization is achieved.
The rx_prbs_err error signal is shared between the PRBS checker and the PRP verifier.
The PRP verifier:
• Searches for a test pattern (two local faults, or all 0s) or its inverse
• Tracks the number of mismatches with a 16-bit error counter
UG-01143
2015.05.11
Pseudo Random Pattern Verifier
5-31
Arria 10 Transceiver PHY Architecture
Altera Corporation
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