User guide

Descrambler
The descrambler block descrambles received data to regenerate unscrambled data using the x
58
+ x
39
+1
polynomial. Like the scrambler, it operates in asynchronous mode or synchronous mode.
Related Information
Scrambler on page 5-25
Interlaken Frame Synchronizer
The Interlaken frame synchronizer delineates the metaframe boundaries and searches for each of the
framing layer control words: Synchronization, Scrambler State, Skip, and Diagnostic. When four consecu‐
tive synchronization words have been identified, the frame synchronizer achieves the frame locked state.
Subsequent metaframes are then checked for valid synchronization and scrambler state words. If four
consecutive invalid synchronization words or three consecutive mismatched scrambler state words are
received, the frame synchronizer loses frame lock. In addition, the frame synchronizer provides
rx_enh_frame_lock (receiver metaframe lock status) to the FPGA fabric.
Note:
The Interlaken frame synchronizer is available to implement the Interlaken protocol.
64B/66B Decoder and Receiver State Machine
The 64B/66B decoder reverses the 64B/66B encoding process. The decoder block also contains a state
machine (RX SM) designed in accordance with the IEEE802.3-2008 specification. The RX SM checks for a
valid packet structure in the data sent from the remote side. It also performs functions such as sending
local faults to the Media Access Control (MAC)/Reconciliation Sublayer (RS) under reset and substituting
error codes when the 10GBASE-R and 10GBASE-KR PCS rules are violated.
Note:
The 64B/66B decoder is available to implement the 10GBASE-R protocol.
PRBS Checker (Shared between Standard and Enhanced PCSes)
You can use Arria 10 pseudo-random bit stream (PRBS) checker to easily characterize high-speed links
without developing or fully implementing any upper layer of a protocol stack. The PRBS checker in
Arria10 is shared hardened block between the Standard and Enhanced datapaths through the PCS instead
of being two unique instances: one for Standard PCS and one for the Enhanced PCS. Hence, there is only
one set of control signals and registers for using this feature.
You can use the PRBS checker block to verify the pattern generated by the PRBS generator. The PRBS
checker can be configured for two widths of the PCS-PMA interface: 10 bits and 64 bits. PRBS9 is
available in both 10-bit and 64-bit PCS-PMA widths. All other PRBS patterns are available in 64-bit PCS-
PMA width only. The PRBS checker patterns can only be used when the PCS-PMA interface width is
configured to 10 bits or 64 bits.
The pseudo-random bit stream (PRBS) block verifies the pattern generated by the PRBS generator. The
verifier supports the 64-bit PCS-PMA interface. PRBS7 supports 64-bit width only. PRBS9 supports 10-bit
PMA data width to allow testing at a lower data rate.
Table 5-6: Supported PRBS Patterns
PRBS Pattern 10 bit PCS-PMA width 64 bit PCS-PMA width
PRBS7: x
7
+ x
6
+ 1
Yes
PRBS9: x
9
+ x
5
+ 1 Yes Yes
5-30
Descrambler
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Architecture
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