User guide

KR FEC TX Gearbox
The KR FEC TX gearbox converts 65-bit input words to 64-bit output words to interface the KR FEC
encoder with the PMA. This gearbox is different from the TX gearbox used in the Enhanced PCS. The KR
FEC TX gearbox aligns with the FEC block. Because the encoder output (also the scrambler output) has
its unique word size pattern, the gearbox is specially designed to handle that pattern.
Receiver Datapath
RX Gearbox, RX Bitslip, and Polarity Inversion
The RX gearbox adapts the PMA data width to the larger bus width of the PCS channel (Gearbox
Expansion). It supports different ratios (PCS-PMA interface width : FPGA fabric–PCS interface width)
such as 32:66, 40:66, 32:67, 40:67, 40:50, 32:64, 40:64, 40:40, 32:32, 64:64, 67:64, and 66:64 and a bit
slipping feature.
RX bitslip is engaged when the RX block synchronizer or rx_bitslip is enabled to shift the word
boundary. On the rising edge of the bitslip signal of the RX block synchronizer or rx_bitslip from the
FPGA fabric, the word boundary is shifted by 1 bit. Each bit slip removes the earliest received bit from the
received data.
Figure 5-29: RX Bitslip
rx_bitslip is toggled two times, which shifts the rx_parallel_data boundary two bits.
00000001
00000000 00100000 00200000 00400000
tx_parallel_data (hex)
rx_parallel_data (hex)
tx_ready
rx_ready
rx_clkout
rx_bitslip
The receiver gearbox can invert the polarity of the incoming data. This is useful if the receiver signals are
reversed on the board or backplane layout. Enable polarity inversion through the Native PHY IP
Parameter Editor.
Block Synchronizer
The block synchronizer determines the block boundary of a 66-bit word in the case of the 10GBASE-R
protocol or a 67-bit word in the case of the Interlaken protocol. The incoming data stream is slipped one
bit at a time until a valid synchronization header (bits 65 and 66) is detected in the received data stream.
After the predefined number of synchronization headers (as required by the protocol specification) is
detected, the block synchronizer asserts rx_enh_blk_lock (block lock status signal) to other receiver PCS
blocks down the receiver datapath and to the FPGA fabric.
Note:
The block synchronizer is designed in accordance with Interlaken Protocol specification (as
described in Figure 13 of Interlaken Protocol Definition v1.2) and 10GBASE-R protocol specifica‐
tion (as described in IEEE 802.3-2008 clause-49).
Interlaken Disparity Checker
The Interlaken disparity checker examines the received inversion bit inserted by the far end disparity
generator, to determine whether to reverse the inversion process of the Interlaken disparity generation.
Note:
The Interlaken disparity checker is available to implement the Interlaken protocol.
UG-01143
2015.05.11
Receiver Datapath
5-29
Arria 10 Transceiver PHY Architecture
Altera Corporation
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