User guide

Table 5-5: Inversion Bit Definition
Bit 66 Interpretation
0 Bits [63:0] are not inverted; the receiver processes this word without modification
1 Bits [63:0] are inverted; the receiver inverts the bits before processing this word
Note: The Interlaken disparity generator is available to implement the Interlaken protocol.
TX Gearbox, TX Bitslip and Polarity Inversion
The TX gearbox adapts the PCS data width to the smaller bus width of the PCS-PMA interface (Gearbox
Reduction). It supports different ratios (FPGA fabric-PCS Interface Width: PCS-PMA Interface Width)
such as 66:32, 66:40, 67:32, 67:40, 50:40, 64:32, 64:40, 40:40, 32:32, 64:64, 67:64, and 66:64. The gearbox
mux selects a group of consecutive bits from the input data bus depending on the gearbox ratio and the
data valid control signals.
Data valid generation logic is essential for gearbox operation. Each block of data is accompanied by
tx_enh_data_valid (data valid signal) which “qualifies” the block as valid or not. The data valid toggling
pattern is dependent on the data width conversion ratio. For example, if the ratio is 66:40, the data valid
signal is high in 20 out of 33 cycles or approximately 2 out of 3 cycles and the pattern repeats every 33
tx_clkout (TX low-speed parallel clock) cycles.
Figure 5-26: 66:40 Data Valid Pattern
rd_clk of TX FIFO
(tx_clkout)
tx_enh_data_valid
The TX gearbox also has a bit slipping feature to adjust the data skew between channels. The TX parallel
data is slipped on the rising edge of tx_enh_bitslip before it is passed to the PMA. The maximum
number of the supported bitslips is PCS data width-1 and the slip direction is from MSB to LSB and from
current to previous word.
Figure 5-27: TX Bitslip
tx_enh_bitslip = 2 and PCS width of gearbox is 67
You can use transmitter data polarity inversion to invert the polarity of every bit of the input data word to
the serializer in the transmitter path. The inversion has the same effect as swapping the positive and
negative signals of the differential TX buffer. This is useful if these signals are reversed on the board or
backplane layout. Enable polarity inversion through the Native PHY IP Parameter Editor.
UG-01143
2015.05.11
TX Gearbox, TX Bitslip and Polarity Inversion
5-27
Arria 10 Transceiver PHY Architecture
Altera Corporation
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