User guide

Figure 5-24: Asynchronous Scrambler in Serial Implementation
S0 S1 S38 S39 S56
OUT
IN
S2 S57
In synchronous mode, the scrambler is initially reset to different programmable seeds on each lane. The
scrambler then runs by itself. Its current state is XOR’d with the data to generate scrambled data. A data
checker in the scrambler monitors the data to determine if it should be scrambled or not. If a synchroni‐
zation word is found, it is transmitted without scrambling. If a Scrambler State Word is detected, the
current scramble state is written into the 58-bit scramble state field in the Scrambler State Word and sent
over the link. The receiver uses this scramble state to synchronize the descrambler. The seed is automati‐
cally set for Interlaken protocol.
Figure 5-25: Synchronous Scrambler Showing Different Programmable Seeds
37 38 570
IN
OUT
LFSR Seed
S0 S37 S38 S57
Interlaken Disparity Generator
The Interlaken disparity generator block is in accordance with the Interlaken protocol specification and
provides a DC-balanced data output.
The Interlaken protocol solves the unbounded baseline wander, or DC imbalance, of the 64B/66B coding
scheme used in 10Gb Ethernet by inverting the transmitted data. The disparity generator monitors the
transmitted data and makes sure that the running disparity always stays within a ±96-bit bound. It adds
the 67th bit (bit 66) to signal the receiver whether the data is inverted or not.
5-26
Interlaken Disparity Generator
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Architecture
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