User guide
The CRC-32 calculation covers most of the metaframe, including the diagnostic word, except the
following:
• Bits [66:64] of each word
• 58-bit scrambler state within the scrambler state word
• 32-bit CRC-32 field within the diagnostic word
Figure 5-20: Interlaken CRC-32 Generator
The Interlaken CRC-32 generator implements the Interlaken protocol.
Interlaken
CRC-32
Generator
Payload
Total Data for CRC-32 Calculation
Metaframe
From the Interlaken Frame Generator
Metaframes with Embedded
CRC-32 Code to Scrambler
Di
Di
Sy
0 0 066676767
SB SKSy SB SK Payload
Total Data for CRC-32 Calculation
Calculated CRC-32 Value
Inserted in the 32 Bits
of Diagnostic Word
Sy
31 066
SB SKSy SB SK
64B/66B Encoder and Transmitter State Machine
The 64B/66B encoder is used to achieve DC-balance and sufficient data transitions for clock recovery. It
encodes 64-bit XGMII data and 8-bit XGMII control into 10GBASE-R 66-bit control or data blocks in
accordance with Clause 49 of the IEEE802.3-2008 specification.
The 66-bit encoded data contains two overhead sync header bits that the receiver PCS uses for block
synchronization and bit-error rate (BER) monitoring. The sync header is 01 for data blocks and 10 for
control blocks. Sync headers are not scrambled and are used for block synchronization. (The sync headers
00 and 11 are not used, and generate an error if seen.) The remainder of the block contains the payload.
The payload is scrambled and the sync header bypasses the scrambler.
The encoder block also has a state machine (TX SM) designed in accordance with the IEEE802.3-2008
specification. The TX SM ensures valid packet construction on data sent from the MAC layer. It also
performs functions such as transmitting local faults under reset, as well as transmitting error codes when
the 10GBASE-R PCS rules are violated.
Note:
The 64B/66B encoder is available to implement the 10GBASE-R protocol.
5-22
64B/66B Encoder and Transmitter State Machine
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Architecture
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