User guide

The TX FIFO supports the following operating modes:
• Phase Compensation mode
• Register mode
• Interlaken mode
• Basic mode
Related Information
Reconfiguration Interface and Dynamic Reconfiguration on page 6-1
Phase Compensation Mode
In Phase Compensation mode, the TX FIFO decouples phase variations between the FPGA fabric and
transceiver clock domains. In this mode, the TX FIFO compensates for the phase difference between the
read and write clocks. You can use tx_coreclkin (FPGA fabric clock) or tx_clkout (TX parallel low-
speed clock) to clock the write side of the TX FIFO. tx_clkout clocks the read side of the TX FIFO.
Note:
The TX FIFO write clock frequency and read clock frequency depend on the gearbox ratio,
tx_enh_data_valid control signal. When TX FIFO is used in phase compensation mode, TX
FIFO write clock frequency and read clock frequency depends on uneven gear ratios (like 64:40,
64:32 etc.), tx_enh_data_valid control signal. For the even gear ratios (like 64:64, 40:40 etc.), tie
tx_enh_data_valid to one. Write clock is tx_coreclkin and by conecting tx_clkout to
tx_coreclkin tx_clockout can also be used as write clock.
For example, when using the 40:40 gearbox ratio and a data rate of 10 Gbps, the tx_clkout frequency is
250 MHz and the tx_coreclkin frequency is 250 MHz. The tx_clkout frequency is 257.8125 MHz in
10GBASE-R mode when using the 66:40 gearbox ratio. tx_coreclkin must run at 156.25 MHz.
Note:
You must control the tx_enh_data_valid signal based on the gearbox ratio to avoid overflow or
underflow in the TX FIFO.
Note: Phase Compensation can also be used in double-width mode, where the FPGA fabric data width is
doubled to allow the FPGA fabric clock to run at half rate. The single/double width mode is set in
the Native PHY Parameter Editor. Refer to the PLLs and Clock Networks chapter for details about
the clock frequencies when using FIFO single and double width modes.
Related Information
• PLLs and Clock Networks on page 3-1
Register Mode
In Register mode, tx_parallel_data (data), tx_control (indicates whether tx_parallel_data is a data
or control word), and tx_enh_data_valid (data valid) are registered at the FIFO output. The FIFO in
register mode has one register stage or one parallel clock latency.
Note:
Altera recommends a minimum of 32-words for the soft FIFO depth in the FPGA fabric for the
following conditions:
• When the Enhanced PCS TX FIFO is set to register mode.
• When using the recovered clock to drive the core logics.
• When there is no soft FIFO being generated along with the IP Catalog.
5-20
Phase Compensation Mode
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Architecture
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