User guide

Figure 5-18: Enhanced PCS Datapath Diagram
Transmitter Enhanced PCSTransmitter PMA
Receiver PMA
Receiver Enhanced PCS
TX
Gearbox
tx_serial_data
Serializer
Interlaken
Disparity Generator
Scrambler
Parallel Clock
PRBS
Generator
PRP
Generator
rx_serial_data
Deserializer
CDR
Descrambler
Interlaken
Disparity Checker
Block
Synchronizer
Interlaken
Frame Sync
RX
Gearbox
PRBS
Verifier
Transcode
Decoder
KR FEC RX
Gearbox
KR FEC
Decoder
KR FEC
Block Sync
KR FEC
Descrambler
Parallel Clock
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Clock Divider
Parallel and Serial Clocks
Clock Generation Block (CGB)
Serial Clock
Input Reference Clock
ATX PLL
fPLL
CMU PLL
64B/66B Decoder
and RX SM
10GBASE-R
BER Checker
PRP
rx_pma_div_clkout
tx_pma_div_clkout
Verifier
rx_coreclkin
rx_clkout
Enhanced PCS
TX FIFO
Enhanced PCS
RX FIFO
Interlaken
Frame Generator
Interlaken
CRC32 Generator
Interlaken
CRC32 Checker
64B/66B Encoder
and TX SM
TX
Data &
Control
RX
Data &
Control
FPGA
Fabric
tx_coreclkin
tx_clkout
KR FEC
TX Gearbox
KR FEC
Scrambler
KR FEC
Encoder
Transcode
Encoder
Related Information
Implementing Protocols in Arria 10 Transceivers on page 2-1
Transmitter Datapath
Enhanced PCS TX FIFO (Shared with Standard PCS and PCIe Gen3 PCS)
The Enhanced PCS TX FIFO provides an interface between the transmitter channel PCS and the FPGA
fabric. The TX FIFO can operate for phase compensation between the channel PCS and FPGA fabric. You
can also use the TX FIFO as an elastic buffer to control the input data flow, using tx_enh_data_valid.
The TX FIFO also allows channel bonding. The TX FIFO has a width of 73 bits and a depth of 16 words.
The TX FIFO partially full and empty thresholds can also be set through the Transceiver and PLL Address
Map. Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for more details.
UG-01143
2015.05.11
Transmitter Datapath
5-19
Arria 10 Transceiver PHY Architecture
Altera Corporation
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