User guide

Figure 5-17: Reverse Loopback Path/Post CDR
The reverse loopback path sets the transmitter buffer to transmit data fed directly from the CDR
recovered data. Data from the serializer is ignored by the transmitter buffer.
Transmitter
Buffer
Serial
Data
Transmitter Serial
Differential Output
Data
Transmitter PMA
FPGA
Fabric
Receiver
PCS
Deserializer
Parallel
Data
Parallel
Data
Serial
Data
Receiver PMA
CDR
Serial
Data
Receiver
Buffer
FPGA
Fabric
Transmitter
PCS
Serializer
Transmitter
PLL
Parallel
Data
Parallel
Data
Serial
Clock
Input
Reference
Clock
Clock
Generation
Block
Parallel
Clock
Receiver Serial
Differential Input
Data
Reverse
Loopback
Serial Clock
Parallel Clock
Arria 10 Enhanced PCS Architecture
You can use the Enhanced PCS to implement multiple protocols that operate at around 10 Gbps or higher
line rates.
The Enhanced PCS provides the following functions:
• Performs functions common to most serial data industry standards, such as word alignment,
encoding/decoding, and framing, before data is sent or received off-chip through the PMA
• Handles data transfer to and from the FPGA fabric
• Internally handles data transfer to and from the PMA
• Provides frequency compensation
• Performs channel bonding for multi-channel low skew applications
5-18
Arria 10 Enhanced PCS Architecture
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Architecture
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