User guide

rx_set_locktoref rx_set_locktodata CDR Lock Mode
1 0 Manual-RX CDR LTR
X 1 Manual-RX CDR LTD
Deserializer
The deserializer block clocks in serial input data from the receiver buffer using the high-speed serial
recovered clock and deserializes the data using the low-speed parallel recovered clock. The deserializer
forwards the deserialized data to the receiver PCS or FPGA fabric.
The deserializer supports the following deserialization factors: 8, 10, 16, 20, 32, 40, and 64.
Figure 5-14: Deserializer Block Diagram
The deserializer block sends out the LSB of the input data first.
Dn D2 D1 D0
Serial
Data
LSB
Deserializer
Parallel
Clock
Clock
Serial
Dn
D2
D1
D0
Parallel
Data
Loopback
The PMA supports serial, diagnostic, and reverse loopback paths.
5-16
Deserializer
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Architecture
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