User guide

Protocol Transceiver IP PCS Support Transceiver
Configuration
Rule
(15)
Protocol Preset
(16)
8G/4G/2G/1G Fibre
Channel
Native PHY IP Standard Basic/Custom
(Standard PCS)
User created
EDR Infiniband x1, x4, x12 Native PHY IP
Enhanced (low
latency mode)
PCS Direct
Basic (Enhanced
PCS)
PCS Direct
User created
FDR/FDR-10 Infiniband
x1, x4, x12
Native PHY IP Enhanced Basic (Enhanced
PCS)
User created
SDR/DDR/QDR
Infiniband x1, x4, x12
Native PHY IP Standard Basic/Custom
(Standard PCS)
User created
CPRI 6.0 10.1376 Gbps Native PHY IP Enhanced 10GBASE-R
1588
User created
CPRI 4.2/OBSAI RP3 v4.2 Native PHY IP Standard CPRI (Auto) /
CPRI (Manual)
CPRI 9.8Gbps Auto Mode
CPRI 9.8 Gbps Manual
Mode
SRIO 2.2/1.3 Native PHY IP Standard Basic/Custom
with Rate
Match(Standard
PCS)
Serial Rapid IO 1.25 Gbps
SAS 3.0 Native PHY IP Enhanced Basic (Enhanced
PCS)
User created
(15)
For more information about Transceiver Configuration Rules, refer to Using the Arria 10 Transceiver
Native PHY IP Core on page 2-17.
(16)
For more information about Protocol Presets, refer to Using the Arria 10 Transceiver Native PHY IP Core
on page 2-17.
(17)
Hard IP for PCI Express is also available as a separate IP core.
(18)
The 1G/10GbE and 10GBASE-KR PHY IP core includes the necessary soft IP for link training, auto speed
negotiation, and sequencer functions.
(19)
Needs a user created IP for link training, auto speed negotiation, and sequencer functions.
(20)
A Transmit PCS soft bonding logic required for multi-lane bonding configuration and a Receive PCS multi-
lane deskew control logic is provided in the design example.
(21)
To implement 40GBASE-R/100GBASE-R using the Low Latency Enhanced PCS preset, change the number
of data channels to four and select appropriate PCS- FPGA Fabric and PCS-PMA width.
(22)
To implement 100GBASE-R via CAUI using the Low Latency Enhanced PCS preset, change the number of
data channels to 10 and select appropriate PCS-FPGA Fabric and PCS-PMA width.
(23)
Low Latency GT protocol preset requires some modification to implement OTU-4 (100G) via OTL4.4/CEI-
28G-VSR.
UG-01143
2015.05.11
Arria 10 Transceiver Protocols and PHY IP Support
2-15
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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