User guide

How to Enable CTLE and DFE
Table 5-2: Summary of Receiver Equalization Modes
Receiver Equalization Modes
CTLE adaptation mode Triggered, Manual
DFE adaptation mode Continuous, Manual, Disabled
Number of fixed DFE taps 3,7
Note: For a high speed link that requires both CTLE and DFE, you can use all combinations of CTLE and
DFE modes shown in the table above. For example: Use CTLE in manual or triggered mode with
DFE in continuous mode.
Configuration Methods
Configure the modes using one of the following methods:
Method 1 - Using Arria 10 Transceiver Native PHY IP Core
1. Select the CTLE/DFE mode in the RX PMA tab of the PHY IP Core
2. Compile the design
3. Choose one the following:
• If CTLE or DFE is in Manual mode, set the CTLE gain value or DFE taps using one of the following
ways:
1. Assignment Editor/.qsf- Recompile the design to make these values effective.
Refer to Analog Parameter Settings for more details about Receiver Equalization Settings.
2. Avalon-MM (AVMM) Interface - Value written through AVMM interface take precedence over
values defined in Assignment Editor. Use this method to dynamically set values and hence avoid
re-compilation.
Refer to Arria 10 Transceiver Register Map for more details on AVMM interface and to perform
dynamic read/write.
• If CTLE is in Triggered Adaptation mode or DFE is in Continuous Adaptation mode, start
adaptation using the following sequence:
1. Provide access to AVMM bus to start adaptation:. Write logic high into
adp_adapt_control_sel
2. Write logic low into adapt_reset
3. Write logic high into adapt_reset
4. Write logic low into adapt_start
5. Write logic high into adapt_start
• Refer to the Arria 10 Register Map and Arria 10 Adaptation Tool for more details on these
specific registers to start Adaptation and to read back the converged CTLE gain and DFE tap
values.
Method 2 - Using AVMM Interface
1. Any changes you make using AVMM interface take precedence over what was configured in Native
PHY IP GUI and/or Assignment Editor.
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How to Enable CTLE and DFE
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Architecture
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