User guide

Figure 5-9: Signal ISI
ISI+
ISI-
Precursor Cursor Postcursor
Notes:
• An ideal pulse response is a single data point at the cursor.
• Real world pulse response is non-zero before the cursor (precursor) and after the
cursor (postcursor).
• ISI occurs when the data sampled at precursor or postcursor is not zero.
The DFE circuit stores delayed versions of the data. The stored bit is multiplied by a coefficient and then
summed with the incoming signal. The polarity of each coefficient is programmable.
The DFE architecture supports seven fixed taps.
The seven fixed taps translate to the DFE capable of removing the ISI from the next 7 bits, beginning from
the current bit.
5-10
Decision Feedback Equalization (DFE)
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Architecture
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