User guide

Note: On-chip biasing circuitry is available only if you select OCT. If you select external termination, you
must implement off-chip biasing circuitry to establish the V
CM
at the receiver input buffer.
Programmable Differential On-Chip Termination (OCT)
Receiver buffers include programmable on-chip differential termination of 85Ω, 100Ω, or OFF.
You can disable OCT and use external termination. If you select external termination, the receiver
common mode is tri-stated. Common mode is based on the external termination connection. You will
also need to implement off-chip biasing circuitry to establish the V
CM
at the receiver buffer.
Signal Detector
You can enable the optional signal threshold detection circuitry. If enabled, this option senses whether the
signal level present at the receiver input buffer is above the signal detect threshold voltage that you
specified in the assignment editor.
Continuous Time Linear Equalization (CTLE)
The CTLE boosts the signal that is attenuated due to channel characteristics. Each receiver buffer has
independently programmable equalization circuits. These equalization circuits amplify the high-
frequency component of the incoming signal by compensating for the low-pass characteristics of the
physical medium. The CTLE can support both DC and AC gain.
DC gain circuitry provides an equal amplification to the incoming signal across the frequency spectrum.
AC gain circuitry provides amplification to the high-frequency spectrum gain of the incoming signal.
Arria 10 transceivers support dual mode CTLE.
High Gain Mode
High gain mode is mainly for backplane application up to 17.4 Gbps. This mode provides both AC and
DC gain. There are two bandwidth settings available for this mode.
Full Bandwidth—This mode has a peaking frequency of 6.25 GHz offering AC gain around 15 dB.
Medium Bandwidth—This mode has a peaking frequency of 3.125 GHz offering AC gain around 20
dB.
5-6
Programmable Differential On-Chip Termination (OCT)
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Architecture
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