User guide

Figure 5-5: Receiver PMA Block Diagram
FPGA
Fabric
Receiver
PCS
Deserializer
Parallel
Data
Parallel
Data
Serial
Data
Serial Clock
Receiver PMA
CDR
Serial
Data
Receiver
Buffer
Parallel Clock
Receiver Serial
Differential Input
Data
Receiver Buffer
The receiver input buffer receives serial data from rx_serial_data and feeds the serial data to the clock
data recovery (CDR) unit and deserializer.
Figure 5-6: Receiver Buffer
RX
V
CM
From Serial Data
Input Pins
(rx_serial_data)
VGA
Adaptive Parametric
Tuning Engine
CTLE
To ODI, CDR
and DFE
RX
Termination
85Ω, 100Ω, OFF
The receiver buffer supports the following features:
• Programmable common mode voltage (V
CM
)
• Programmable differential On-Chip Termination (OCT)
• Signal Detector
• Continuous Time Linear Equalization (CTLE)
• Variable Gain Amplifiers (VGA)
• Adaptive Parametric Tuning Engine
• Decision Feedback Equalization (DFE)
• On-Die Instrumentation (ODI)
Programmable Common Mode Voltage (V
CM
)
The receiver buffer has on-chip biasing circuitry to establish the required V
CM
at the receiver input.
The Quartus II software automatically chooses the optimal setting for RX V
CM
.
UG-01143
2015.05.11
Receiver Buffer
5-5
Arria 10 Transceiver PHY Architecture
Altera Corporation
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