User guide

Protocol Transceiver IP PCS Support Transceiver
Configuration
Rule
(15)
Protocol Preset
(16)
SONET STS-96 (5G) via
OIF SFI-5.1s
Native PHY IP Enhanced Basic/Custom
(Standard PCS)
SONET/SDH OC-96
SONET/SDH STS-48/
STM-16 (2.5G) via SFP/
TFI-5.1
Native PHY IP Standard Basic/Custom
(Standard PCS)
SONET/SDH OC-48
SONET/SDH STS-12/
STM-4 (0.622G) via SFP/
TFI-5.1
Native PHY IP Standard Basic/Custom
(Standard PCS)
SONET/SDH OC-12
Intel QPI 1.1/2.0 Native PHY IP PCS Direct PCS Direct User created
SD-SDI/HD-SDI/3G-SDI Native PHY IP Standard Basic/Custom
(Standard PCS)
3G/HD SDI NTSC
3G/HD SDI PAL
Vx1 Native PHY IP Standard Basic/Custom
(Standard PCS)
User created
DisplayPort Native PHY IP Standard Basic/Custom
(Standard PCS)
User created
1.25G/ 2.5G
10G GPON/EPON
Native PHY IP Enhanced Basic (Enhanced
PCS)
User created
2.5G/1.25G GPON/EPON Native PHY IP Standard Basic/Custom
(Standard PCS)
User created
16G/10G Fibre Channel Native PHY IP Enhanced Basic (Enhanced
PCS)
User created
(15)
For more information about Transceiver Configuration Rules, refer to Using the Arria 10 Transceiver
Native PHY IP Core on page 2-17.
(16)
For more information about Protocol Presets, refer to Using the Arria 10 Transceiver Native PHY IP Core
on page 2-17.
(17)
Hard IP for PCI Express is also available as a separate IP core.
(18)
The 1G/10GbE and 10GBASE-KR PHY IP core includes the necessary soft IP for link training, auto speed
negotiation, and sequencer functions.
(19)
Needs a user created IP for link training, auto speed negotiation, and sequencer functions.
(20)
A Transmit PCS soft bonding logic required for multi-lane bonding configuration and a Receive PCS multi-
lane deskew control logic is provided in the design example.
(21)
To implement 40GBASE-R/100GBASE-R using the Low Latency Enhanced PCS preset, change the number
of data channels to four and select appropriate PCS- FPGA Fabric and PCS-PMA width.
(22)
To implement 100GBASE-R via CAUI using the Low Latency Enhanced PCS preset, change the number of
data channels to 10 and select appropriate PCS-FPGA Fabric and PCS-PMA width.
(23)
Low Latency GT protocol preset requires some modification to implement OTU-4 (100G) via OTL4.4/CEI-
28G-VSR.
2-14
Arria 10 Transceiver Protocols and PHY IP Support
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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