User guide

Signal Name Direction Clock Domain Description
rx_digital-
reset[<n> -1:0]
Output Synchronous to the
Transceiver PHY
Reset Controller
input clock.
Digital reset for RX. The width of this signal
depends on the number of channels. This signal
is asserted when any of the following
conditions is true:
• reset is asserted
• rx_analogreset is asserted
• rx_cal_busy is asserted
• rx_is_lockedtodata is deasserted and rx_
manual is deasserted
When all of these conditions are false, the reset
counter begins its countdown for deassertion of
rx_digitalreset.
rx_analogreset
[<n>-1:0]
Output Synchronous to the
Transceiver PHY
Reset Controller
input clock.
Analog reset for RX. When asserted, resets the
RX CDR and the RX PMA blocks of the
transceiver PHY. This signal is asserted when
any of the following conditions is true:
• reset is asserted
• rx_cal_busy is asserted
The width of this signal depends on the number
of channels.
rx_ready[<n>-1:0] Output Synchronous to the
Transceiver PHY
Reset Controller
input clock.
Status signal to indicate when the RX reset
sequence is complete. This signal is deasserted
while the RX reset is active. It is asserted a few
clock cycles after the deassertion of rx_
digitalreset. Some protocol implementa‐
tions may require you to monitor this signal
prior to sending data. The width of this signal
depends on the number of RX channels.
pll_powerdown[<p>-
1:0]
Output Synchronous to the
Transceiver PHY
Reset Controller
input clock.
Asserted to power down a transceiver PLL
circuit. When asserted, the selected TX PLL is
reset.
Transceiver PHY Reset Controller Resource Utilization
This section describes the estimated device resource utilization for two configurations of the transceiver
PHY reset controller. The exact resource count varies by Quartus II version number, as well as by
optimization options.
Table 4-6: Reset Controller Resource Utilization
Configuration Combination ALUTs Logic Registers
Single transceiver channel approximately 50 approximately 50
UG-01143
2015.05.11
Transceiver PHY Reset Controller Resource Utilization
4-17
Resetting Transceiver Channels
Altera Corporation
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