User guide

Signal Name Direction Clock Domain Description
rx_cal_busy[<n> -
1:0]
Input Asynchronous This is calibration status signal from the
Transceiver PHY IP core. When asserted, the
initial calibration is active. When deasserted,
calibration has completed. It will not be
asserted if you manually re-trigger the calibra‐
tion IP. This signal gates the RX reset sequence.
The width of this signals depends on the
number of RX channels.
rx_is_lockedto-
data[<n>-1:0]
Input Synchronous to
CDR
Provides the rx_is_lockedtodata status from
each RX CDR. When asserted, indicates that a
particular RX CDR is ready to receive input
data. If you do not choose separate controls for
the RX channels, these inputs are ANDed
together internally to provide a single status
signal.
tx_manual[<n>-1:0] Input Asynchronous This optional signal places tx_digitalreset
controller under automatic or manual control.
When asserted, the associated tx_digital-
reset controller logic does not automatically
respond to deassertion of the pll_locked
signal. However, the initial tx_digitalreset
sequence still requires a one-time rising edge
on pll_locked before proceeding. When
deasserted, the associated tx_digitalreset
controller automatically begins its reset
sequence whenever the selected pll_locked
signal is deasserted.
rx_manual[<n> -
1:0]
Input Asynchronous This optional signal places rx_digitalreset
logic controller under automatic or manual
control. In manual mode, the rx_digital-
reset controller does not respond to the
assertion or deassertion of the rx_is_
lockedtodata signal. The rx_digitalreset
controller asserts rx_ready when the rx_is_
lockedtodata signal is asserted.
clock Input N/A A free running system clock input to the
Transceiver PHY Reset Controller from which
all internal logic is driven. If a free running
clock is not available, hold reset until the
system clock is stable.
reset Input Asynchronous Asynchronous reset input to the Transceiver
PHY Reset Controller. When asserted, all
configured reset outputs are asserted. Holding
the reset input signal asserted holds all other
reset outputs asserted. An option is available to
synchronize with the system clock.
UG-01143
2015.05.11
Transceiver PHY Reset Controller Interfaces
4-15
Resetting Transceiver Channels
Altera Corporation
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