User guide

Protocol Transceiver IP PCS Support Transceiver
Configuration
Rule
(15)
Protocol Preset
(16)
OTU-4 (100G) via
OTL4.10/OIF SFI-S
Native PHY IP Enhanced Basic (Enhanced
PCS)
SFI-S 64:64 4x11.3 Gbps
OTU-3 (40G) via OTL3.4/
OIF SFI-5.2/SFI-5.1
Native PHY IP Enhanced Basic (Enhanced
PCS)
User created
OTU-2 (10G) via SFP+/
SFF-8431/CEI-11G
Native PHY IP Enhanced Basic (Enhanced
PCS)
User created
OTU-2 (10G) via OIF SFI-
5.1s
Native PHY IP Enhanced Basic (Enhanced
PCS)
User created
OTU-1 (2.7G) Native PHY IP Standard Basic/Custom
(Standard PCS)
User created
SONET/SDH STS-768/
STM-256 (40G) via OIF
SFI-5.2/STL256.4
Native PHY IP Enhanced Basic (Enhanced
PCS)
User created
SONET/SDH STS-768/
STM-256 (40G) via OIF
SFI-5.1
Native PHY IP Enhanced Basic (Enhanced
PCS)
User created
SONET/SDH STS-192/
STM-64 (10G) via SFP+/
SFF-8431/CEI-11G
Native PHY IP Enhanced Basic (Enhanced
PCS)
User created
SONET/SDH STS-192/
STM-64 (10G) via OIF SFI-
5.1s/SxI-5/SFI-4.2
Native PHY IP Enhanced Basic (Enhanced
PCS)
User created
(15)
For more information about Transceiver Configuration Rules, refer to Using the Arria 10 Transceiver
Native PHY IP Core on page 2-17.
(16)
For more information about Protocol Presets, refer to Using the Arria 10 Transceiver Native PHY IP Core
on page 2-17.
(17)
Hard IP for PCI Express is also available as a separate IP core.
(18)
The 1G/10GbE and 10GBASE-KR PHY IP core includes the necessary soft IP for link training, auto speed
negotiation, and sequencer functions.
(19)
Needs a user created IP for link training, auto speed negotiation, and sequencer functions.
(20)
A Transmit PCS soft bonding logic required for multi-lane bonding configuration and a Receive PCS multi-
lane deskew control logic is provided in the design example.
(21)
To implement 40GBASE-R/100GBASE-R using the Low Latency Enhanced PCS preset, change the number
of data channels to four and select appropriate PCS- FPGA Fabric and PCS-PMA width.
(22)
To implement 100GBASE-R via CAUI using the Low Latency Enhanced PCS preset, change the number of
data channels to 10 and select appropriate PCS-FPGA Fabric and PCS-PMA width.
(23)
Low Latency GT protocol preset requires some modification to implement OTU-4 (100G) via OTL4.4/CEI-
28G-VSR.
UG-01143
2015.05.11
Arria 10 Transceiver Protocols and PHY IP Support
2-13
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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