User guide

Transceiver Block pll_powerdown tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset
Transmitter
Standard PCS
Yes
Transmitter
Enhanced PCS
Yes
Transmitter PMA Yes
Transmitter PCIe
Gen3 PCS
Yes
Using the Altera Transceiver PHY Reset Controller
Altera's Transceiver PHY Reset Controller is a configurable IP core that resets transceivers mainly in
response to PLL lock activity. You can use this IP core rather than creating your own user-coded reset
controller. You can define a custom reset sequence for the IP core. You can also modify the IP cores's
generated clear text Verilog HDL file to implement custom reset logic.
The Transceiver PHY Reset Controller handles all transceiver reset sequencing and supports the following
options:
• Separate or shared reset controls per channel in response to PLL lock activity
• Separate controls for the TX and RX channels and PLLs
• Synchronization of the reset inputs
• Hysteresis for PLL locked status inputs
• Configurable reset timing
• Automatic or manual reset recovery mode in response to loss of PLL lock
You should create your own reset controller if the Transceiver PHY Reset Controller IP does not meet
your requirements, especially when you require independent transceiver channel reset. The following
figure illustrates the typical use of the Transceiver PHY Reset Controller in a design that includes a
transceiver PHY instance and the transmit PLL.
UG-01143
2015.05.11
Using the Altera Transceiver PHY Reset Controller
4-9
Resetting Transceiver Channels
Altera Corporation
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