User guide

Figure 4-7: Reset Sequence Timing Diagram for Transceiver when CDR is in Manual Lock Mode
rx_digitalreset
rx_set_locktoref
rx_set_locktodata
rx_is_lockedtoref
rx_is_lockedtodata
rx_analogreset
rx_ready
Status Signals
Control Signals
t
LTD_Manual
min 4 μs
1
2
2
4
5
6
3
t
LTR_LTD_manual
min 15 μs
1
1
1
1
2
4
Transceiver Blocks Affected by Reset and Powerdown Signals
You must reset the digital PCS each time you reset the analog PMA or PLL. However, you can reset the
digital PCS block alone.
Table 4-3: Transceiver Blocks Affected by Specified Reset and Powerdown Signals
Transceiver Block pll_powerdown tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset
CMU PLL Yes
ATX PLL Yes
fPLL Yes
CDR Yes
Receiver Standard
PCS
Yes
Receiver Enhanced
PCS
Yes
Receiver PMA Yes
Receiver PCIe Gen3
PCS
Yes
4-8
Transceiver Blocks Affected by Reset and Powerdown Signals
UG-01143
2015.05.11
Altera Corporation
Resetting Transceiver Channels
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