User guide

Protocol Transceiver IP PCS Support Transceiver
Configuration
Rule
(15)
Protocol Preset
(16)
100GBASE-R via CAUI Native PHY IP Enhanced Basic (Enhanced
PCS)
Low Latency Enhanced
PCS
(22)
100GBASE-R via CAUI
with FEC
Native PHY IP Enhanced Basic w/KR FEC User created
XAUI XAUI PHY IP Soft PCS Not applicable Not applicable
SPAUI Native PHY IP Standard and
Enhanced
Basic/Custom
(Standard PCS)
Basic (Enhanced
PCS)
User created
DDR XAUI Native PHY IP Standard and
Enhanced
Basic/Custom
(Standard PCS)
Basic (Enhanced
PCS)
User created
Interlaken (CEI-6G/
11G)
(20)
Native PHY IP Enhanced Interlaken
Interlaken 10x12.5Gbps
Interlaken 6x10.3Gbps
Interlaken 1x6.25Gbps
OTU-4 (100G) via OTL4.4/
CEI-25G/28G VSR/SR
Native PHY IP
Enhanced PCS
(low latency
mode)
PCS Direct
Basic (Enhanced
PCS) / PCS
Direct
Low Latency GT
(23)
(15)
For more information about Transceiver Configuration Rules, refer to Using the Arria 10 Transceiver
Native PHY IP Core on page 2-17.
(16)
For more information about Protocol Presets, refer to Using the Arria 10 Transceiver Native PHY IP Core
on page 2-17.
(17)
Hard IP for PCI Express is also available as a separate IP core.
(18)
The 1G/10GbE and 10GBASE-KR PHY IP core includes the necessary soft IP for link training, auto speed
negotiation, and sequencer functions.
(19)
Needs a user created IP for link training, auto speed negotiation, and sequencer functions.
(20)
A Transmit PCS soft bonding logic required for multi-lane bonding configuration and a Receive PCS multi-
lane deskew control logic is provided in the design example.
(21)
To implement 40GBASE-R/100GBASE-R using the Low Latency Enhanced PCS preset, change the number
of data channels to four and select appropriate PCS- FPGA Fabric and PCS-PMA width.
(22)
To implement 100GBASE-R via CAUI using the Low Latency Enhanced PCS preset, change the number of
data channels to 10 and select appropriate PCS-FPGA Fabric and PCS-PMA width.
(23)
Low Latency GT protocol preset requires some modification to implement OTU-4 (100G) via OTL4.4/CEI-
28G-VSR.
2-12
Arria 10 Transceiver Protocols and PHY IP Support
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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