User guide

When Is Reset Required?
You can reset the transmitter (TX) and receiver (RX) data paths independently or together. The
recommended reset sequence requires reset and initialization of the PLL driving the TX or RX channels,
as well as the TX and RX datapaths. A reset may be required after any of the following events:
Table 4-1: Reset Conditions
Event Reset Requirement
Device power up and configura‐
tion
Requires reset to the transceiver PHY and the associated PLLs to a
known initialize state.
PLL reconfiguration Requires reset to ensure that the PLL acquires lock at optimal
operating conditions and also to reset the PHY.
PLL reference clock frequency
change
Requires reset to the PLL to ensure PLL lock. You must also reset the
PHY.
PLL recalibration Requires reset to the PLL to ensure PLL lock. You must also reset the
PHY.
PLL lock loss or recovery Requires reset after a PLL acquired lock from a momentary loss of
lock. You must also reset the PHY.
Channel dynamic reconfiguration Requires reset to the PLL and the PHY to initialize blocks for the new
configuration.
Optical module connection Requires reset of RX to ensure lock of incoming data.
RX CDR lock mode change Requires reset of the RX channel any time the RX clock and data
recovery (CDR) block switches from lock-to-reference to lock-to-
data RX channel.
How Do I Reset?
You reset a transceiver PHY or PLL by integrating a reset controller in your system design to initialize the
PCS and PMA blocks. You can save time by using the Altera-provided Transceiver PHY Reset Controller
IP core, or you can implement your own reset controller that follows the recommended reset sequence.
You can design your own reset controller if you require individual control of each signal for reset or need
additional control or status signals as part of the reset functionality.
4-2
When Is Reset Required?
UG-01143
2015.05.11
Altera Corporation
Resetting Transceiver Channels
Send Feedback