User guide

Connection Guidelines for PLL and Clock Networks
• For 12.5 Gbps Interlaken with a bonded group of 10 channels, connect the tx_bonding_clocks to the
transceiver PLL's tx_bonding_clocks output port. Make this connection for all 10 bonded channels.
This connection uses a master CGB and the x6 / xN clock line to reach all the channels in the bonded
group.
• Connect the tx_serial_clk port of the first two instances of the 10GBASE-KR PHY IP to the
tx_serial_clk port of PLL instance 1 (ATX PLL at 5.1625 GHz). This connection uses the x1 clock
line within the transceiver bank.
• Connect the tx_serial_clk port of the remaining two instances of the 10GBASE-KR PHY IP to the
tx_serial_clk port of the PLL instance 2 (ATX PLL at 5.1625 GHz). This connection uses the x1
clock line within the transceiver bank.
• Connect the three tx_serial_clk ports for the custom multi-data rate PHY IP as follows:
• Connect tx_serial_clk0 port to the tx_serial_clk port of PLL instance 2 (ATX PLL at 5.1625
GHz). This PLL instance is shared with the two 10GBASE-KR PHY IP channels and also uses the
x1 clock line within the transceiver bank.
• Connect the tx_serial_clk1 port to the tx_serial_clk port of the PLL instance 3 (ATX PLL at
4.9 GHz). This connection uses the x1 clock line within the transceiver bank.
• Connect the tx_serial_clk2 port to the tx_serial_clk port of the PLL instance 4 (ATX PLL at
4.9 GHz). This connection uses the x1 clock line within the transceiver bank.
• Connect the 1.25 Gbps Gigabit Ethernet non-bonded PHY IP instance to the tx_serial_clk port of
the PLL instance 5. Make this connection twice, one for each channel. This connection uses the x1
clock line within the transceiver bank.
• Connect the PCIe Gen3 bonded group of 8 channels as follows:
• Connect the tx_bonding_clocks of the PHY IP to the tx_bonding_clocks port of the
Transceiver PLL Instance 6. Make this connection for each of the 8 bonded channels.
• Connect the pipe_sw_done of the PHY IP to the pipe_sw port of the transceiver PLL instance 6.
• Connect the pll_pcie_clk port of the PLL instance 5 to the PHY IP's pipe_hclk_in port.
• Connect tx_serial_clk port of the PLL instance 5 to the mcgb_aux_clk0 port of the PLL instance
6. This connection is required as a part of the PCIe speed negotiation protocol.
Timing Closure Recommendations
Register mode is harder to close timing in Arria10 devices. Altera recommends using negative edge
capture on the RX side for periphery to core transfers greater than 240MHz. To be specific, capture on a
negative edge clock in the core and then immediately transfer to a positive edge clock.
• Use PCLK clock network for frequencies up to 250 Mhz.
• H/V clocking is recommended for higher frequencies.
For core to periphery transfers on TX targeting higher frequencies (beyond 250 MHz), Altera
recommends using TX Fast Register mode as the PCS FIFO mode. This is the mode with PCLK that
should be used by default for most 10GbE 1588 modes and 9.8 Gbps/10.1376 Gbps CPRI mode.
• You can use H/V routing to get up to 320 MHz in Register mode for the highest speed grade.
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Timing Closure Recommendations
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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